82801FB Datasheet, PDF (273/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.51
7.1.52
OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value: 00h
Attribute:
R/W
Size:
8-bit
Bit
Description
7:2 Reserved
Coprocessor Error Enable (CEN) — R/W.
1
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel^® ICH6 generates IRQ13 internally and holds it until an I/O port F0h
write. It will also drive IGNNE# active.
APIC Enable (AEN) — R/W.
0
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value: 00000000h
Attribute:
Size:
R/W, R/WLO
32-bit
Bit
Description
31:5 Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
4
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed.
Writes will be dropped and reads will not return any guaranteed data. Bit reset on system
reset.
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
3
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed.
Writes will be dropped and reads will not return any guaranteed data. Bit reset on system
reset.
Upper 128 Byte Enable (UE) — R/W.
2
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
1:0 Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
273