82801FB Datasheet, PDF (70/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-18. Miscellaneous Signals (Sheet 2 of 2)
Name
Type
Description
TP[0]
(Desktop Only) /
BATLOW#
I
Test Point 0: This signal must have an external pull-up to VccSus3_3.
(Mobile Only)
TP[1]
(Desktop Only) /
DPRSLPVR#
O
Test Point 1: Route signal to a test point.
(Mobile Only)
TP[2]
(Desktop Only) /
DPSLP#
O
Test Point 2: Route signal to a test point.
(Mobile Only)
TP[3]
I Test Point 3: Route signal to a test point.
TP[4]
(Desktop Only) /
DPRSTP#
O
Test Point 4: Route signal to a test point.
(Mobile Only)
2.19 AC ’97/Intel^® High Definition Audio Link
Table 2-19. AC ’97/Intel^® High Definition Audio Link Signals
Name
ACZ_RST#
ACZ_SYNC
ACZ_BIT_CLK
ACZ_SDOUT
ACZ_SDIN[2:0]
Type
O
O
I/O
O
I
Description
AC ’97/Intel High Definition Audio Reset: This signal is a master hardware
reset to external codec(s).
AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz fixed rate
sample sync to the codec(s). Also used to encode the stream number.
AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data clock generated
by the external codec(s). This signal has an integrated pull-down resistor (see
Note below).
Intel High Definition Audio Bit Clock Output: This signal is a 24.000 MHz
serial data clock generated by the Intel High Definition Audio controller (the Intel^®
ICH6). This signal has an integrated pull-down resistor so that ACZ_BIT_CLK
does not float when an Intel High Definition Audio codec (or no codec) is
connected but the signals are temporarily configured as AC ’97.
AC ’97/Intel High Definition Audio Serial Data Out: This signal is a serial TDM
data output to the codec(s). This serial output is double-pumped for a bit rate of
48 Mb/s for Intel High Definition Audio
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a functional
strap. See Section 2.22.1 for more details. There is a weak integrated
pull-down resistor on the ACZ_SDOUT pin.
AC ’97/Intel High Definition Audio Serial Data In [2:0]: This signal is a serial
TDM data inputs from the three codecs. The serial input is single-pumped for a bit
rate of 24 Mb/s for Intel High Definition Audio. These signals have integrated pull-
down resistors, which are always enabled.
NOTES:
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.
2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode
of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to
1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet