82801FB Datasheet, PDF (15/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
9.1.19
9.1.20
9.1.21
9.1.22
9.1.23
9.1.24
9.1.25
9.1.26
BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ........................................335
SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0) ..............................................................................................336
PDPR—PCI Decode Policy Register
(PCI-PCI—D30:F0) ..............................................................................................337
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0) ..............................................................................................338
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0) ..............................................................................................339
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0) ..............................................................................................340
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0) ..............................................................................................340
SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)..............................341
10 LPC Interface Bridge Registers (D31:F0)...................................................................343
10.1 PCI Configuration Registers (LPC I/F—D31:F0) ..............................................................343
10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .....................................344
10.1.2 DID—Device Identification Register (LPC I/F—D31:F0)......................................344
10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)....................................345
10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)..............................................346
10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)...................................347
10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ....................................347
10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..........................................347
10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).........................................347
10.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) .................................348
10.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ......................................348
10.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ...................................348
10.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .............................349
10.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) .................................349
10.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) .......................350
10.1.15 GC—GPIO Control Register (LPC I/F — D31:F0) ...............................................350
10.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) ...............................................................................................351
10.1.17 SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0) ...............................................................................................352
10.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0) ...............................................................................................353
10.1.19 LPC_I/O_DEC—I/O Decode Ranges Register
(LPC I/F—D31:F0) ...............................................................................................354
10.1.20 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)....................................355
10.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0) ...............................................................................................356
10.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0) ...............................................................................................356
10.1.23 FWH_SEL1—Firmware Hub Select 1 Register
(LPC I/F—D31:F0) ...............................................................................................357
10.1.24 FWH_SEL2—Firmware Hub Select 2 Register
(LPC I/F—D31:F0) ...............................................................................................358
10.1.25 FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0) ...............................................................................................359
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
15