82801FB Datasheet, PDF (668/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
Bit
Description
FIFO Error Interrupt Enable — R/W. This bit controls whether the occurrence of a FIFO error
3 (overrun for input or underrun for output) will cause an interrupt or not. If this bit is not set, bit 3in the
Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped.
Interrupt on Completion Enable — R/W. This bit controls whether or not an interrupt occurs when
2 a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register
will be set, but the interrupt will not occur.
Stream Run (RUN) — R/W.
0 = When cleared to 0, the DMA engine associated with this input stream will be disabled. The
hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must
1
read a 0 from this bit before modifying related control registers or restarting the DMA engine.
1 = When set to 1, the DMA engine associated with this input stream will be enabled to transfer
data from the FIFO to the main memory. The SSYNC bit must also be cleared in order for the
DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit
is set.
Stream Reset (SRST) — R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready
to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before
accessing any of the stream registers.
0 _{1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers}
(except the SRST bit itself) and FIFO’s for the corresponding stream are reset. After the stream
hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software
must read a 1 from this bit to verify that the stream is in reset. The RUN bit must be cleared
before SRST is asserted.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet