82801FB Datasheet, PDF (251/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.6
7.1.7
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Default Value: 00000001h
Attribute:
Size:
RO
32-bit
Bit
31:24
23
22:16
15
14
13:8
7:0
Description
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table since the
arbitration is fixed.
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and therefore this field
is not used.
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just
advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port
arbitration.
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Default Value: 800000FFh
Attribute:
Size:
R/W, RO
32-bit
Bit
31
30:27
26:24
23:20
19:17
16
15:8
7:1
0
Description
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and cannot be
disabled.
Reserved
Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this virtual channel.
Reserved
Port Arbitration Select (PAS) — R/W. Indicates which port table is being programmed. The root
complex takes no action on this setting since the arbitration is fixed and there is no arbitration
table.
Load Port Arbitration Table (LAT) — RO. The root complex does not implement an arbitration
table for this virtual channel.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates which transaction
classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to
the virtual channel.
Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
251