82801FB Datasheet, PDF (250/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.3
7.1.4
7.1.5
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Default Value: 00000001h
Attribute:
Size:
RO
32-bit
Bit
31:24
23:0
Description
VC Arbitration Table Offset (ATO) — RO. This bit indicates that no table is present for VC
arbitration since it is fixed.
Reserved
PVC—Port Virtual Channel Control Register
Offset Address: 000C–000Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16-bit
Bit
15:04
3:1
0
Description
Reserved
VC Arbitration Select (AS) — RO. This bit indicates which VC should be programmed in the VC
arbitration table. The root complex takes no action on the setting of this field since there is no
arbitration table.
Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed should be
loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on
reads.
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Default Value: 0000h
Attribute:
Size:
RO
16-bit
Bit
15:01
0
Description
Reserved
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the VC
Arbitration table when it is being updated. This field is always 0 in the root complex since there is
no VC arbitration table.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet