82801FB Datasheet, PDF (257/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.23
7.1.24
7.1.25
ILCL—Internal Link Capabilities List Register
Offset Address: 01A0–01A3h
Default Value: 00010006h
Attribute:
Size:
RO
32-bit
Bit
31:20
19:16
15:0
Description
Next Capability Offset (NEXT) — RO. This field indicates this is the last item in the list.
Capability Version (CV) — RO. This field indicates the version of the capability structure.
Capability ID (CID) — RO. This field indicates this is capability for DMI.
LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h
Default Value: 00012441h
Attribute:
Size:
RO, R/WO
32-bit
Bit
31:18
17:15
14:12
11:10
9:4
3:0
Description
Reserved
L1 Exit Latency (EL1) — L1 not supported on DMI.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less than 256
ns.
Active State Link PM Support (APMS) — R/WO. This field indicates that L0s is supported on DMI.
Maximum Link Width (MLW) — This field indicates the maximum link width is 4 ports.
Maximum Link Speed (MLS) — This field indicates the link speed is 2.5 Gb/s.
LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value: 0000h
Attribute:
Size:
R/W
16-bit
Bit
Description
15:8 Reserved
7
Extended Synch (ES) — R/W. When set, forces extended transmission of FTS ordered sets
when exiting L0s prior to entering L0.
6:2 Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI should enter
L0s.
00 = Disabled
1:0
01 = L0s entry enabled
10 = Reserved
11 = Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
257