82801FB Datasheet, PDF (412/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Bit
Description
PME_B0_STS — R/W. This bit will be set to 1 by the ICH6 when any internal device with PCI
Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally,
if the PME_B0_EN bit is set, and the system is in an S0 state, then the setting of the
PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_STS bit is
13
set, and the system is in an S1–S4 state (or S5 state due to SLP_TYP and SLP_EN), then the
setting of the PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not
set) will be generated. If the system is in an S5 state due to power button override, then the
PME_B0_STS bit will not cause a wake event or SCI.
12
11
10
(Desktop
Only)
10
(Mobile
Only)
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
USB3_STS — R/W.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset.
This bit is set when USB UHCI controller #3 needs to cause a wake. Additionally if the
USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event.
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set,
and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or
SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or
S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI will be generated. If the system is in an S5 state due to
power button override or a power failure, then PME_STS will not cause a wake event or SCI.
Reserved
BATLOW_STS — R/WC. (Mobile Only) Software clears this bit by writing a 1 to it.
0 = BATLOW# Not asserted
1 = Set by hardware when the BATLOW# signal is asserted.
PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
• The PME event message was received on one or more of the PCI Express* ports
• An Assert PMEGPE message received from the (G)MCH via DMI
NOTES:
1. The PCI WAKE# pin has no impact on this bit.
9
2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a de-assert
PMEGPE message must be received prior to the software write in order for the bit to be
cleared.
3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI
will remain active.
4. A race condition exists where the PCI Express device sends another PME message because
the PCI Express device was not serviced within the time when it must resend the message.
This may result in a spurious interrupt, and this is comprehended and approved by the PCI
Express* Specification, Revision 1.0a. The window for this race condition is approximately 95-
105 milliseconds.
RI_STS — R/WC.
8
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
412
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet