82801FB Datasheet, PDF (398/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.4
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
A9h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
This register is used to enable new C-state related modes.
Bit
Description
7 SCRATCHPAD (SP) — R/W.
6:5 Reserved
Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME bit
(D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.
0 = The ICH6 will not attempt to automatically return to a previous C3 or C4 state.
4
1 = When this bit is a 1 and Intel^® ICH6 observes that there are no bus master requests, it can
return to a previous C3 or C4 state.
NOTE: This bit is separate from the PUME bit to cover cases where latency issues permit POPUP
but not POPDOWN.
Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH6 behaves like ICH5, in that bus
master traffic is a break event, and it will return from C3/C4 to C0 based on a break event. See
Chapter 5.14.5 for additional details on this mode.
3 ^{0 = The ICH6 will treat Bus master traffic a break event, and will return from C3/C4 to C0 based on}
a break event.
1 = When this bit is a 1 and ICH6 observes a bus master request, it will take the system from a C3
or C4 state to a C2 state and auto enable bus masters. This will let snoops and memory access
occur.
Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.
0 = The ICH6 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from PCI, PCI
Express* and internal bus masters.
1 = When this bit is a 1, ICH6 will not set the BM_STS if there is bus master activity from PCI, PCI
Express and internal bus masters.
2 _NOTES:
1. If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the BM_STS bit will
remain set. Software will still need to clear the BM_STS bit.
2. It is expected that if the PUME bit (this register, bit 3) is set, the BM_STS_ZERO_EN bit should
also be set. Setting one without the other would mainly be for debug or errata workaround.
3. BM_STS will be set by LPC DMA or LPC masters, even if BM_STS_ZERO_EN is set.
1:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet