82801FB Datasheet, PDF (422/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.3.17 SS_CNT— Intel SpeedStep^® Technology
Control Register (Mobile Only)
I/O Address:
Default Value
Lockable:
Power Well:
PMBASE +50h
01h
No
Core
Attribute:
Size:
Usage:
R/W (special)
8-bit
ACPI/Legacy
Note:
Writes to this register will initiate an Intel SpeedStep technology transition that involves a
temporary transition to a C3-like state in which the STPCLK# signal will go active. An Intel
SpeedStep technology transition always occur on writes to the SS_CNT register, even if the value
written to SS_STATE is the same as the previous value (after this “transition” the system would
still be in the same Intel SpeedStep technology state). If the SS_EN bit is 0, then writes to this
register will have no effect and reads will return 0.
Bit
Description
7:1 Reserved
SS_STATE (Intel SpeedStep^® technology State) — R/W (Special). When this bit is read, it returns
the last value written to this register. By convention, this will be the current Intel SpeedStep
technology state. Writes to this register causes a change to the Intel SpeedStep technology state
indicated by the value written to this bit. If the new value for SS_STATE is the same as the previous
0 ^{value, then transition will still occur.}
0 = High power state.
1 = Low power state
NOTE: This is only a convention because the transition is the same regardless of the value written
to this bit.
10.8.3.18 C3_RES— C3 Residency Register (Mobile Only)
I/O Address:
Default Value
Lockable:
Power Well:
PMBASE +54h
00000000h
No
Core
Attribute:
Size:
Usage:
RW/RO
32-bit
ACPI/Legacy
Software may only write this register during system initialization to set the state of the
C3_RESIDENCY_MODE bit. It must not be written while the timer is in use.
Bit
Description
31
30:24
23:0
C3_RESEDENCY_MODE — RW.
When this bit is 0, the C3_RESIDENCY counter field will automatically clear upon entry into the C3
or C4 state. When this bit is 1, the C3_RESIDENCY counter will not automatically clear upon entry
into the C3 or C4 state.
Reserved
C3_RESIDENCY — RO. The value in this field increments at the same rate as the Power
Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automatically resets to 0
at the point when the Lvl3 or Lvl4 read occurs. If the C3_RESIDENCY_MODE bit is set, the register
does not reset when the Lvl3 or Lvl4 read occurs. In either mode, it increments while STP_CPU# is
active (i.e. the processor is in a C3 or C4 state). This field will roll over in the same way as the PM
Timer, however the most significant bit is NOT sticky.
Software is responsible for reading this field before performing the Lvl3/4 transition. Software must
also check for rollover if the maximum time in C3/C4 could be exceeded.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet