82801FB Datasheet, PDF (441/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.5
11.1.6
11.1.7
RID—Revision Identification Register (IDE—D31:F1)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 6 (ICH6) Family Specification Update for
the value of the Revision ID Register
PI—Programming Interface Register (IDE—D31:F1)
Address Offset: 09h
Default Value: 8Ah
Attribute: RO, R/W
Size:
8 bits
Bit
Description
7 This read-only bit is a 1 to indicate that the ICH6 supports bus master operation
6:4 Reserved. Hardwired to 000b.
3
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary controller supports
both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary IDE channel
is operating in.
2
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
1
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller supports
both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary IDE channel is
operating in.
0
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
SCC—Sub Class Code Register (IDE—D31:F1)
Address Offset: 0Ah
Default Value: 01h
Attribute: RO
Size:
8 bits
Bit
Description
Sub Class Code (SCC) — RO.
7:0
01h = IDE device, in the context of a mass storage device.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
441