82801FB Datasheet, PDF (445/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.18
INTR_LN—Interrupt Line Register (IDE—D31:F1)
Address Offset: 3Ch
Default Value: 00h
Attribute: R/W
Size:
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. This field is used to communicate to software the interrupt line that
the interrupt pin is connected to.
11.1.19
INTR_PN—Interrupt Pin Register (IDE—D31:F1)
Address Offset: 3Dh
Default Value: See Register Description
Attribute: RO
Size:
8 bits
Bit
Description
7:0
Interrupt Pin — RO. This field reflects the value of D31IP.PIP (Chipset Configuration
Registers:Offset 3100h:bits 7:4).
11.1.20
IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)
Address Offset: 40–41h
Default Value: 0000h
Attribute: R/W
Size:
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
Bit
Description
15
14
13:12
11:10
9:8
IDE Decode Enable (IDE) — R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the
Command register must be set in order for this bit to have any effect.
0 = Disable.
1 = Enables the ICH6 to decode the Command (1F0–1F7h) and Control (3F6h) Blocks.
This bit also effects the memory decode range for IDE Expansion.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI
clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
445