82801FB Datasheet, PDF (303/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.2.10
PMDR—Power Management Driver Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
The ICH6’s internal LAN controller provides an indication in the PMDR that a wake-up event has
occurred.
Bit
Description
Link Status Change Indication — R/WC.
7 _{0 = Software clears this bit by writing a 1 to it.}
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
0 = Software clears this bit by writing a 1 to it.
6 _{1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable}
bit in the configuration command and the PME Enable bit in the Power Management Control/
Status Register.
Interesting Packet — R/WC.
5 ^{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the
LAN controller packet filters.
4:3 Reserved
2 ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.
TCO Request — R/WC.
1 _{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set to 1b when the LAN controller is busy with TCO activity.
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power Management
Control/Status Register (PMCSR).
0 _{0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the PMCSR and}
de-asserts the PME signal.
1 = Set upon a wake-up event, independent of the PME Enable bit.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
303