82801FB Datasheet, PDF (720/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

High Precision Event Timer Registers
Bit
Description
Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
3
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to
generate a periodic interrupt.
Timers 1, 2: Hardwired to 0. Writes have no affect.
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set to enable timer
n to cause an interrupt when it times out.
2
1 = Enable.
0 = Disable (Default). The timer can still count and generate appropriate status bits, but will not
cause an interrupt.
Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.
0 =The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If
another interrupt occurs, another edge will be generated.
1
1 =The timer interrupt is level triggered. This means that a level-triggered interrupt is generated.
The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt
Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will
remain active.
0
Reserved. These bits will return 0 when read.
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any unimplemented
registers will return an undetermined value.
720
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet