82801FB Datasheet, PDF (16/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
10.1.26 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)............................................................................................... 360
10.1.27 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)............................................................................................... 361
10.2 DMA I/O Registers (LPC I/F—D31:F0)............................................................................. 361
10.2.1 DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)............................................................................... 363
10.2.2 DMABASE_CC—DMA Base and Current Count Registers
(LPC I/F—D31:F0)............................................................................................... 363
10.2.3 DMAMEM_LP—DMA Memory Low Page Registers
(LPC I/F—D31:F0)............................................................................................... 364
10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .................................. 364
10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0).......................................... 365
10.2.6 DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0)............................................................................................... 365
10.2.7 DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)............................................................................................... 366
10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0) ......................................... 366
10.2.9 DMA Master Clear Register (LPC I/F—D31:F0).................................................. 367
10.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) .......................... 367
10.2.11 DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0)............................................................................................... 367
10.3 Timer I/O Registers (LPC I/F—D31:F0)............................................................................ 368
10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) .................................... 369
10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0)............................................................................................... 371
10.3.3 Counter Access Ports Register (LPC I/F—D31:F0)............................................. 372
10.4 8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)............................................................................................................ 372
10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ................................................. 372
10.4.2 ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0)............................................................................................... 373
10.4.3 ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)............................................................................................... 374
10.4.4 ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0).................................................................... 374
10.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0).................................................................... 375
10.4.6 ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0)............................................................................................... 375
10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0) ................................................................................ 376
10.4.8 OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0)............................................................................................... 376
10.4.9 OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0)............................................................................................... 377
10.4.10 ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)............................................................................................... 378
10.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)............................................................................................... 379
10.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0) ........................................ 380
10.5.1 APIC Register Map (LPC I/F—D31:F0) ............................................................... 380
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet