82801FB Datasheet, PDF (120/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.5.1.9 I/O Cycles
For I/O cycles targeting registers specified in the ICH6’s decode ranges, the ICH6 performs I/O
cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit
transfers. If the processor attempts a 16-bit or 32-bit transfer, the ICH6 breaks the cycle up into
multiple 8-bit transfers to consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH6 returns a value
of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up
resistors would keep the bus high if no device responds.
5.5.1.10 Bus Master Cycles
The ICH6 supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin
Count Interface Specification, Revision 1.1. The ICH6 has two LDRQ# inputs, and thus supports
two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or
Bus Master 1 (0011b).
Note: The ICH6 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only
perform memory read or memory write cycles.
5.5.1.11 LPC Power Management
CLKRUN# Protocol (Mobile Only)
The CLKRUN# protocol is same as the PCI specification. Stopping the PCI clock stops the LPC
clock.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ#
low or tri-state it. ICH6 shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the
ICH6 drives LFRAME# low, and tri-states (or drive low) LAD[3:0].
Note:
The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there
is at least 30 µs from LPCPD# assertion to LRST# assertion. This specification explicitly states
that this protocol only applies to entry/exit of low power states which does not include
asynchronous reset events. The ICH6 asserts both SUS_STAT# (connects to LPCPD#) and
PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK,
or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol.
5.5.1.12 Configuration and Intel^® ICH6 Implications
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH6 includes
several decoders. During configuration, the ICH6 must be programmed with the same decode
ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration
space.
Note:
The ICH6 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device
if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are
not part of normal system operation, but may be encountered as part of platform validation testing
using custom test fixtures.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet