82801FB Datasheet, PDF (145/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.12.2
5.12.3
5.12.4
5.12.5
Interrupts
The real-time clock interrupt is internally routed within the ICH6 both to the I/O APIC and the
8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH6, nor is it shared with
any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance
Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked.
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
configuration space. If the locking bits are set, the corresponding range in the RAM will not be
readable or writable. A write cycle to those locations will have no effect. A read cycle to those
locations will not return the location’s actual value (resultant value is undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS
and allow it to relock the RAM range.
Century Rollover
The ICH6 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions from
99 to 00. Upon detecting the rollover, the ICH6 sets the NEWCENTURY_STS bit (TCOBASE +
04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update
registers in the RTC RAM that are associated with century value. If the system is in a sleep state
(S1–S5) when the century rollover occurs, the ICH6 also sets the NEWCENTURY_STS bit, but no
SMI# is generated. When the system resumes from the sleep state, BIOS should check the
NEWCENTURY_STS bit and update the century value in the RTC RAM.
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an ICH6-based platform can be done by using a jumper on RTCRST# or
GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low.
Using RTCRST# to clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of
those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to
ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the
RTC power well will be set to their default state. BIOS can monitor the state of this bit, and
manually clear the RTC CMOS array once the system is booted. The normal position would cause
RTCRST# to be pulled up through a weak pull-up resistor. Table 5-20 shows which bits are set to
their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper
to be moved and then replaced—all while the system is powered off. Then, once booted, the
RTC_PWR_STS can be detected in the set state.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
145