82801FB Datasheet, PDF (244/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Register and Memory Mapping
Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Memory Range
Target
Dependency/Comments
4 KB anywhere in 4-GB
range
1 KB anywhere in 4-GB
range
512 B anywhere in 4-GB
range
256 B anywhere in 4-GB
range
512 B anywhere in 64-bit
addressing space
FED0 X000h–FED0 X3FFh
All other
Integrated LAN
Controller¹
Enable via BAR in Device 29:Function 0 (Integrated
LAN Controller)
USB EHCI Controller ²
Enable via standard PCI mechanism (Device 29,
Function 7)
AC ’97 Host Controller Enable via standard PCI mechanism (Device 30,
(Mixer)
Function 2)
AC ’97 Host Controller Enable via standard PCI mechanism (Device 30,
(Bus Master)
Function 3)
Intel High Definition Enable via standard PCI mechanism (Device 30,
Audio Host Controller Function 1)
High Precision Event
Timers ²
BIOS determines the “fixed” location which is one of
four, 1-KB ranges where X (in the first column) is 0h,
1h, 2h, or 3h.
PCI
None
NOTES:
1. Only LAN cycles can be seen on PCI.
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event
Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur.
3. PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Configuration Registers:Offset
3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits have no effect.
6.4.1
Boot-Block Update Scheme
The ICH6 supports a “top-block swap” mode that has the ICH6 swap the top block in the Firmware
Hub (the boot block) with another location. This allows for safe update of the Boot Block (even if a
power failure occurs). When the “TOP_SWAP” Enable bit is set, the ICH6 will invert A16 for
cycles targeting Firmware Hub space. When this bit is 0, the ICH6 will not invert A16. This bit is
automatically set to 0 by RTCRST#, but not by PLTRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block, and the block
immediately below the top block is reserved for doing boot-block updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top
2. Software checks that the copied block is correct. This could be done by performing a
checksum calculation.
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the Firmware Hub.
processor access to FFFF_0000h through FFFF_FFFFh will be directed to FFFE_0000h
through FFFE_FFFFh in the Firmware Hub, and processor accesses to FFFE_0000h through
FFFE_FFFF will be directed to FFFF_0000h through FFFF_FFFFh.
4. Software erases the top block
5. Software writes the new top block
6. Software checks the new top block
7. Software clears the TOP_SWAP bit
8. Software sets the Top_Swap Lock-Down bit
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet