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82801FB Datasheet, PDF (429/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family | |||
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LPC Interface Bridge Registers (D31:F0)
10.9.9
TCO_WDCNTâTCO Watchdog Control Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 0Eh
00h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
Watchdog Status (WDSTATUS) â R/W. The value written to this register will be sent in the Alert
7:0
On LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
10.9.10
SW_IRQ_GENâSoftware IRQ Generation Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 10h
11h
Core
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
IRQ12_CAUSE â R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by
1 the ICH6âs SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ12
assertions from a SERIRQ device.
IRQ1_CAUSE â R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
0 the ICH6âs SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ1
assertions from a SERIRQ device.
10.9.11
TCO_TMRâTCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +12h
0004h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:10
9:0
Reserved
TCO Timer Initial Value â R/W. Value that is loaded into the timer each time the TCO_RLD register
is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer is
clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to
613.8 seconds. Note: The timer has an error of ± 1 tick (0.6s).
The TCO Timer will only count down in the S0 state.
Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
429
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