82801FB Datasheet, PDF (41/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
„ SMBus
— New: Flexible SMBus/SMLink architecture
to optimize for ASF
— Provides independent manageability bus
through SMLink interface
— Supports SMBus 2.0 Specification
— Host interface allows processor to
communicate via SMBus
— Slave interface allows an internal or external
Microcontroller to access system resources
— Compatible with most two-wire components
that are also I²C compatible
„ High Precision Event Timers
— Advanced operating system interrupt
scheduling
„ Timers Based on 82C54
— System timer, Refresh request, Speaker tone
output
„ Real-Time Clock
— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter
implementation
„ System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon
detection of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— Supports ability to disable external devices
„ Interrupt Controller
— Supports up to eight PCI interrupt pins
— Supports PCI 2.3 Message Signaled
Interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24
interrupts
— Supports Processor System Bus interrupt
delivery
„ 1.5 V operation with 3.3 V I/O
— 5 V tolerant buffers on IDE, PCI, and Legacy
signals
„ Integrated 1.5 V Voltage Regulator (INTVR) for
the Suspend and LAN wells
„ Integrated 2.5 V Regulator for Vcc2_5
„ Firmware Hub I/F supports BIOS Memory size
up to 8 Mbytes
„ Low Pin Count (LPC) I/F
— Supports two Master/DMA devices.
— Support for Security Device (Trusted
Platform Module) connected to LPC.
„ GPIO
— TTL, Open-Drain, Inversion
„ Package 31x31 mm 609 mBGA
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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