82801FB Datasheet, PDF (166/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.14.9.5
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH6
immediately transitions to an S5 state. However, since the processor has overheated, it does not
respond to the ICH6’s STPCLK# pin with a stop grant special cycle. Therefore, the ICH6 does not
wait for one. Immediately upon seeing THRMTRIP# low, the ICH6 initiates a transition to the S5
state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a
power button override.
It is extremely important that when a THRMTRIP# event occurs, the ICH6 power down
immediately without following the normal S0 -> S5 path. This path may be taken in parallel, but
ICH6 must immediately enter a power down state. It does this by driving SLP_S3#, SLP_S4#, and
SLP_S5# immediately after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very unlikely)
that components around it, such as the ICH6, are no longer executing cycles properly. Therefore, if
THRMTRIP# goes active, and the ICH6 is relying on state machine logic to perform the power
down, the state machine may not be working, and the system will not power down.
The ICH6 follows this flow for THRMTRIP#.
1. At boot (PLTRST# low), THRMTRIP# ignored.
2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and
SLP_S5# assert, and normal sequence of sleep machine starts.
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if
THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event.
4. If S5 state reached, go to step #1, otherwise stay here. If the ICH6 never reaches S5, the ICH6
does not reboot until power is cycled.
During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and
PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle
reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK = 0, or VRMPWRGD/
VGATE = 0.
Note:
A thermal trip event will:
• Set the AFTERG3_EN bit
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving
message and not set due to SMBAlert
5.14.9.6
BMBUSY# (Mobile Only)
The BMBUSY# signal is an input from a graphics component to indicate if it is busy. If prior to
going to the C3 state, the BMBUSY# signal is active, then the BM_STS bit will be set. If after
going to the C3 state, the BMBUSY# signal goes back active, the ICH6 will treat this as if one of
the PCI REQ# signals went active. This is treated as a break event.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet