82801FB Datasheet, PDF (305/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.2.13
SMB_PCI—SMB via PCI Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Fh
Default Value: 27h
Attribute:
Size:
R/W, RO
8 bits
Software asserts SREQ when it wants to isolate the PCI-accessible SMBus to the ASF registers/
commands. It waits for SGNT to be asserted. At this point SCLI, SDAO, SCLO, and SDAI can be
toggled/read to force ASF controller SMBus transactions without affecting the external SMBus.
After all operations are completed, the bus is returned to idle (SCLO=1b,SDAO=1b, SCLI=1b,
SDAI=1b), SREQ is released (written 0b). Then SGNT goes low to indicate released control of the
bus. The logic in the ASF controller only asserts or de-asserts SGNT at times when it determines
that it is safe to switch (all SMBuses that are switched in/out are idle).
When in isolation mode (SGNT=1), software can access the ICH6 SMBus slaves that allow
configuration without affecting the external SMBus. This includes configuration register accesses
and ASF command accesses. However, this capability is not available to the external TCO
controller. When SGNT=0, the bit-banging and reads are reflected on the main SMBus and the
PCISML_SDA0, PCISML_SCL0 read only bits.
Bit
Description
7:6 Reserved
5 PCISML_SCLO — RO. SMBus Clock from the ASF controller.
4 PCISML_SGNT — RO. SMBus Isolation Grant from the ASF controller.
3 PCISML_SREQ — R/W. SMBus Isolation Request to the ASF controller.
2 PCISML_SDAO — RO. SMBus Data from the ASF controller.
1 PCISML_SDAI — R/W. SMBus Data to the ASF controller.
0 PCISML_SCLI — R/W. SMBus Clock to the ASF controller.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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