82801FB Datasheet, PDF (33/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
19.1.58 AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
19.1.59 RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
19.1.60 RCTCL — Root Complex Topology Capability List Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
19.1.61 ESD — Element Self Description Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................712
19.1.62 ULD — Upstream Link Description Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................712
19.1.63 ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
19.1.64 PCIECR1 — PCI Express Configuration Register 1
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
19.1.65 PCIECR2 — PCI Express Configuration Register 2
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
20 High Precision Event Timer Registers........................................................................715
20.1 Memory Mapped Registers...............................................................................................716
20.1.1 GCAP_ID—General Capabilities and Identification Register...............................717
20.1.2 GEN_CONF—General Configuration Register....................................................717
20.1.3 GINTR_STA—General Interrupt Status Register ................................................718
20.1.4 MAIN_CNT—Main Counter Value Register.........................................................718
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .........................719
20.1.6 TIMn_COMP—Timer n Comparator Value Register............................................721
21 Ballout Definition .................................................................................................................723
22 Electrical Characteristics .................................................................................................733
22.1 Thermal Specifications .....................................................................................................733
22.2 Absolute Maximum Ratings ..............................................................................................733
22.3 DC Characteristics ............................................................................................................734
22.4 AC Characteristics ............................................................................................................743
22.5 Timing Diagrams...............................................................................................................759
23 Package Information ..........................................................................................................777
24 Testability ...............................................................................................................................779
24.1 XOR Chain Test Mode Description...................................................................................779
24.1.1 XOR Chain Testability Algorithm Example ..........................................................780
24.2 XOR Chain Tables ............................................................................................................781
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
33