82801FB Datasheet, PDF (393/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8 Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
10.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)
Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0. It includes
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)
Offset
Mnemonic
Register Name
Default
Type
A0h
A2h
A4h
A9h
AAh
ABh
ADh
B8–BBh
GEN_PMCON_1 General Power Management Configuration 1
GEN_PMCON_2
GEN_PMCON_3
Cx-STATE_CNF
C4-TIMING_CNT
BM_BREAK_EN
MSC_FUN
GPI_ROUT
General Power Management Configuration 2
General Power Management Configuration 3
Cx State Configuration (Mobile Only).
C4 Timing Control (Mobile Only).
BM_BREAK_EN
Miscellaneous Functionality
GPI Route Control
0000h
R/W, RO,
R/WO
00h
R/W, R/WC
00h
R/W, R/WC
00h
R/W
00h
R/W
00h
R/W
00h
R/W
00000000h
R/W
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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