82801FB Datasheet, PDF (479/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.39
.
SIR84—SATA Indexed Registers Index 84h
(SATA Initialization Register 84h)
Address Offset: Index 84h - 87h
Default Value: 0000001Bh
Attribute:
Size:
R/W
32 bits
Bit
31:6 Reserved.
5:0 BIOS programs this field to 101101b.
Description
12.1.40
.
ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset: C0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved
Secondary Slave Trap (SST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
3 accesses to 170h–177h and 376h. The active device on the secondary interface must be device 1
for the trap and/or SMI# to occur.
Secondary Master Trap (SPT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
2 accesses to 170h–177h and 376h. The active device on the secondary interface must be device 0
for the trap and/or SMI# to occur.
Primary Slave Trap (PST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
1 accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 1 for
the trap and/or SMI# to occur.
Primary Master Trap (PMT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
0 accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 0 for
the trap and/or SMI# to occur.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
479