82801FB Datasheet, PDF (594/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Audio Controller Registers (D30:F2)
Table 16-2. Intel^® ICH6 Audio Mixer Register Configuration
Primary Offset
(Codec ID =00)
5Ah
7Ch
7Eh
Secondary Offset
(Codec ID =01)
DAh
FCh
FEh
Tertiary Offset
(Codec ID =10)
15Ah
17Ch
17Eh
NAMBAR Exposed Registers
(D30:F2)
Vendor Reserved
Vendor ID1
Vendor ID2
NOTE:
1. Software should not try to access reserved registers
2. Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of configuration
register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration register 40h.
3. The tertiary offset is only available through the memory space defined by the MMBAR register.
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ’97
controller. Accesses to these registers do not cause the cycle to be forwarded over the AC-link to
the codec. S/W could access these registers as bytes, word, DWord or qword quantities, but reads
must not cross DWord boundaries.
In the case of the split codec implementation accesses to the different codecs are differentiated by
the controller by using address offsets 00h–7Fh for the primary codec, address offsets 80h–FFh for
the secondary codec and address offsets 100h–17Fh for the tertiary codec.
The Global Control (GLOB_CNT) (D30:F2:2Ch) and Global Status (GLOB_STA) (D30:F2:30h)
registers are aliased to the same global registers in the audio and modem I/O space. Therefore a
read/write to these registers in either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The six channels,
PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their own set of Bus
Mastering registers. The following register descriptions apply to all six channels. The register
definition section titles use a generic “x_” in front of the register to indicate that the register applies
to all six channels. The naming prefix convention used in Table 16-3 and in the register description
I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
Table 16-3. Native Audio Bus Master Control Registers (Sheet 1 of 2)
Offset
00h
04h
05h
06h
08h
0Ah
0Bh
10h
Mnemonic
PI_BDBAR
PI_CIV
PI_LVI
PI_SR
PI_PICB
PI_PIV
PI_CR
PO_BDBAR
Name
PCM In Buffer Descriptor list Base Address
PCM In Current Index Value
PCM In Last Valid Index
PCM In Status
PCM In Position in Current Buffer
PCM In Prefetched Index Value
PCM In Control
PCM Out Buffer Descriptor list Base
Address
Default
00000000h
00h
00h
0001h
0000h
00h
00h
Access
R/W
RO
R/W
R/WC, RO
RO
RO
R/W, R/W (special)
00000000h
R/W
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet