82801FB Datasheet, PDF (630/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.1.4
18.1.5
PCISTS—PCI Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Offset Address: 06–07h
Default Value: 0010h
Attribute:
Size:
RO, R/WC
16 bits
Bit
Description
15
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
14
SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort received.
13
1 = The Intel High Definition Audio controller sets this bit when, as a bus master, it receives a
master abort. When set, the Intel High Definition Audio controller clears the run bit for the
channel that received the abort.
12
Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
11
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.
8
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
7
Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0.
6
Reserved.
5
66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.
4
Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller contains a
capabilities pointer list. The first item is pointed to by looking at configuration offset 34h.
Interrupt Status (IS) — RO.
3
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Note that this bit is not set by an MSI.
2:0 Reserved.
RID—Revision Identification Register
(Intel^® High Definition Audio Controller—D27:F0)
Offset:
Default Value:
08h
See bit description
Attribute:
Size:
RO
8 Bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® ICH6 Family Datasheet Specification Update for the value of
the Revision ID Register
630
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet