82801FB Datasheet, PDF (420/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.3.14 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +38h
0000h
No
Resume
Attribute:
Size:
Usage:
R/W
16-bit
ACPI or Legacy
Bit
Description
Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding GPIO to cause
an SMI#. For these bits to have any effect, the following must be true.
• The corresponding bit in the ALT_GP_SMI_EN register is set.
15:0 _{• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.}
• The corresponding GPIO must be implemented.
NOTE: Mapping is as follows: bit 15 corresponds to GPI[15] ... bit 0 corresponds to GPI[0].
10.8.3.15 ALT_GP_SMI_STS—Alternate GPI SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +3Ah
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
Bit
Description
Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding GPIs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be generated and the
15:0 ^{GPE0_STS bit set:}
• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
All bits are in the resume well. Default for these bits is dependent on the state of the GPI pins.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet