82801FB Datasheet, PDF (447/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.21
IDE_TIMS — IDE Secondary Timing Register
(IDE—D31:F1)
Address Offset: 42–43h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15
14:12
11
10:0
IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode. The IDE I/O
Space Enable bit (D31:F1:04h, bit 0) in the Command register must be set in order for this bit to
have any effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration
register) to individually disable the secondary IDE interface signals, even if the IDE Decode Enable
bit is set.
0 = Disable.
1 = Enables the ICH6 to decode the associated Command Blocks (170–177h) and Control Block
(376h). Accesses to these ranges return 00h, as the secondary channel is not implemented.
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have
no functionality in the ICH6 since a secondary channel does not exist.
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have
no functionality in the ICH6 since a secondary channel does not exist.
11.1.22
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)
Address Offset: 44h
Default Value: 00h
Attribute: R/W
Size:
8 bits
Bit
Description
7:4
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the number of PCI
clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1
data port and bit 14 of the IDE timing register for primary is set.
3:2 _{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the minimum number of
PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the
access is to drive 1 data port and bit 14 of the IDE timing register for primary is set.
1:0 _{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
447