82801FB Datasheet, PDF (356/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.21
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h – 85h
Default Value: 0000h
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Bit
Description
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is aligned on a
128-byte boundary, and must have address lines 31:16 as 0.
15:7
NOTE: This generic decode is for I/O addresses only, not memory addresses. The size of this
range is 128 bytes.
6:1 Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 _{0 = Disable.}
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
10.1.22
GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address: 88h – 89h
Default Value: 0000h
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Bit
Description
Generic I/O Decode Range 2 Base Address (GEN2_BASE) — R/W. This address is aligned on a
16-byte, 32-byte, or 64-byte boundary, and must have address lines 31:16 as 0.
15:4
NOTES:
1. This generic decode is for I/O addresses only, not memory addresses. The size of this range is
16, 32, or 64 bytes.
2. Size of decode range is determined by D31:F0:ADh:bits 5:4.
3:1 Reserved. Read as 0.
Generic I/O Decode Range 2 Enable (GEN2_EN) — R/W.
0 _{0 = Disable.}
1 = Accesses to the GEN2 I/O range will be forwarded to the LPC I/F
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet