82801FB Datasheet, PDF (276/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.55
BUC—Backed Up Control Register
Offset Address: 3414–3414h
Attribute:
R/W
Default Value: 0000001xb (Mobile)
Size:
8-bit
0000000xb (Desktop)
All bits in this register are in the RTC well and only cleared by RTCRST#
Bit
Description
7:3 Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by RSMRST#, but not
PLTRST# nor CF9h writes.
2
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and INIT3_3V# will
go inactive with the same timings as the other processor I/F signals (hold time after
CPURST# inactive).
1
(Mobile)
PATA Reset State (PRS) — R/W.
0 = The reset state of the PATA pins will be driven.
1 = The reset state of the PATA pins will be tri-state.
1
Reserved
(Desktop)
Top Swap (TS) — R/W.
0 = Intel^® ICH6 will not invert A16.
0
1 = ICH6 will invert A16 for cycles going to the BIOS space (but not the feature space) in the
FWH.
If ICH is strapped for Top-Swap (GNT[6]# is low at rising edge of PWROK), then this bit cannot be
cleared by software. The strap jumper should be removed and the system rebooted.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet