82801FB Datasheet, PDF (496/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.3.2.6
PxIE—Port [3:0] Interrupt Enable Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 114h
Attribute:
Port 1: ABAR + 194h (Desktop Only)
Port 2: ABAR + 214h
Port 3: ABAR + 294h (Desktop Only)
00000000h
Size:
R/W, RO
32 bits
This register enables and disables the reporting of the corresponding interrupt to system software.
When a bit is set (‘1’) and the corresponding interrupt condition is active, then an interrupt is
generated. Interrupt sources that are disabled (‘0’) are still reflected in the status registers.
Bit
Description
31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect not supported.
30
Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR (due to a
reception of the error register from a received FIS) are set, the Intel^® ICH6 will generate an interrupt.
29
Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS are set, the
ICH6 will generate an interrupt.
28
Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS are set, the
ICH6 will generate an interrupt.
27
Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the
ICH6 will generate an interrupt.
26
Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and PxIS.INFS is set,
the ICH6 will generate an interrupt.
25 Reserved - Should be written as 0
24
Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set, the ICH6 will
generate an interrupt.
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and PxIS.IPMS are set,
23 the ICH6 will generate an interrupt.
NOTE: Should be written as 0. Port Multiplier not supported by ICH6.
22
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and PxIS.PRCS
is set, the ICH6 shall generate an interrupt.
21:8 Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH6 will generate an
7 ^interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
6
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS are set, the
ICH6 will generate an interrupt.
5
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and PxS.DPS are
set, the ICH6 will generate an interrupt
4
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an unknown FIS
is received, the ICH6 will generate this interrupt.
3
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and PxS.SDBS are
set, the ICH6 will generate an interrupt.
2
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS are set, the
ICH6 will generate an interrupt.
1
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS are set, the
ICH6 will generate an interrupt.
0
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and GHC.IE and
PxS.DHRS are set, the ICH6 will generate an interrupt.
496
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet