82801FB Datasheet, PDF (547/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers are located
after the capabilities registers. The operational register base must be DWord-aligned and is
calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address
of the enhanced host controller register address space (MEM_BASE). Since CAPLENGTH is
always 20h, Table 14-3 already accounts for this offset. All registers are 32 bits in length.
Table 14-3. Enhanced Host Controller Operational Register Address Map
MEM_BASE
+ Offset
Mnemonic
Register Name
Default
Special
Notes
Type
20–23h
24–27h
28–2Bh
2C–2Fh
30–33h
34–37h
38–3Bh
3C–5Fh
60–63h
64–67h
68–6Bh
6C–6Fh
70–73h
74–77h
78–7Bh
7C–7Fh
80–83h
84–9Fh
A0–B3h
B4–3FFh
USB2.0_CMD
USB2.0_STS
USB2.0_INTR
FRINDEX
CTRLDS-
SEGMENT
PERODI-
CLISTBASE
ASYNCLIS-
TADDR
—
CONFIGGLAG
USB 2.0 Command
USB 2.0 Status
USB 2.0 Interrupt Enable
USB 2.0 Frame Index
Control Data Structure Segment
Period Frame List Base Address
Current Asynchronous List
Address
Reserved
Configure Flag
PORT0SC Port 0 Status and Control
PORT1SC Port 1 Status and Control
PORT2SC Port 2 Status and Control
PORT3SC Port 3 Status and Control
PORT4SC Port 4 Status and Control
PORT5SC Port 5 Status and Control
PORT6SC Port 6 Status and Control
PORT7SC
—
—
—
Port 7 Status and Control
Reserved
Debug Port Registers
Reserved
00080000h
00001000h
00000000h
00000000h
00000000h
R/W, RO
R/WC, RO
R/W
R/W,
R/W, RO
00000000h
R/W
00000000h
R/W
0h
00000000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
Undefined
Undefined
Undefined
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
RO
R/W
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
R/W,
R/WC, RO
RO
See register
description
RO
Note:
Software must read and write these registers using only DWord accesses.These registers are
divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are implemented in the core
power well. Unless otherwise noted, the core well registers are reset by the assertion of any of the
following:
• Core well hardware reset
• HCRESET
• D3-to-D0 reset
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
547