82801FB Datasheet, PDF (582/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Audio Controller Registers (D30:F2)
16.1.1
16.1.2
Core well registers not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh – Subsystem ID (SID)
• offset 40h – Programmable Codec ID (PCID)
• offset 41h – Configuration (CFG)
Resume well registers will not be reset by the D3_HOT to D0 transition:
• offset 54h–55h – Power Management Control and Status (PCS)
• Bus Mastering Register: Global Status Register, bits 17:16
• Bus Mastering Register: SDATA_IN MAP register, bits 7:3
VID—Vendor Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
00–01h
8086h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
Description
15:0 Vendor ID. This is a 16-bit value assigned to Intel.
DID—Device Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
02–03h
266Eh
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Device ID.
Description
582
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet