82801FB Datasheet, PDF (156/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.14.5 Dynamic Processor Clock Control
The ICH6 has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various sleep states may also
perform types of non-dynamic clock control.
The ICH6 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3 and C4 (in mobile)
states.
The Dynamic Processor Clock control is handled using the following signals:
• STPCLK#:
• (Mobile Only) STP_CPU#:
• (Mobile Only) CPUSLP#:
• (Mobile Only) DPSLP#
• (Mobile Only) DPRSLPVR:
• (Mobile Only) DPRSTP#:
Used to halt processor instruction stream.
Used to stop processor’s clock
Asserted prior to STP_CPU# (in stop grant mode)
Used to force Deeper Sleep for processor.
Used to lower voltage of VRM during C4 state.
Used to lower voltage of VRM during C4 state
The C1 state is entered based on the processor performing an auto halt instruction.
(Mobile Only) The C2 state is entered based on the processor reading the Level 2 register in the
ICH6. It can also be entered from C3 or C4 states if bus masters require snoops and the PUME bit
(D31:F0: Offset A9h: bit 3) is set.
(Mobile Only) The C3 state is entered based on the processor reading the Level 3 register in the
ICH6 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7). This state can also be
entered after a temporary return to C2 from a prior C3 or C4 state.
(Mobile Only) The C4 state is entered based on the processor reading the Level 4 register in the
ICH6, or by reading the Level 3 register when the C4onC3_EN bit is set. This state can also be
entered after a temporary return to C2 from a prior C4 state.
A C1 state in desktop or a C1, C2, C3 or C4 state in mobile ends due to a Break event. Based on the
break event, the ICH6 returns the system to C0 state.
(Mobile Only) Table 5-28 lists the possible break events from C2, C3 or C4. The break events from
C1 are indicated in the processor’s datasheet.
Table 5-28. Break Events (Mobile Only) (Sheet 1 of 2)
Event
Breaks from
Comment
Any unmasked interrupt goes
active
Any internal event that cause an
NMI or SMI#
C2, C3, C4
IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O
APIC. Since SCI is an interrupt, any SCI will also be a
break event.
C2, C3, C4 Many possible sources
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet