82801FB Datasheet, PDF (334/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.15
9.1.16
9.1.17
9.1.18
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field provides the upper 32-bits
of the prefetchable address base.
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field provides the upper 32-bits
of the prefetchable address limit.
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h
Default Value: 50h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3C–3Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line (vector) the
7:0 interrupt is connected to. No hardware action is taken on this register. Since the bridge does not
generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification.
334
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet