82801FB Datasheet, PDF (666/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.30
IRS—Immediate Command Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 68h
Default Value: 0000h
Attribute:
Size:
R/W, R/WC
16 bits
Bit
Description
15:2 Reserved.
Immediate Result Valid (IRV) — R/WC. This bit is set to 1 by hardware when a new response is
latched into the Immediate Response register (HDBAR + 64). This is a status flag indicating that
1 ^{software may read the response from the Immediate Response register.}
Software must clear this bit by writing a 1 to it before issuing a new command so that the software
may determine when a new response has arrived.
Immediate Command Busy (ICB) — R/W. When this bit is read as 0, it indicates that a new
command may be issued using the Immediate Command mechanism. When this bit transitions from
a 0 to a 1 (via software writing a 1), the controller issues the command currently stored in the
Immediate Command register to the codec over the link. When the corresponding response is
0 ^{latched into the Immediate Response register, the controller hardware sets the IRV flag and clears}
the ICB bit back to 0.
NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism is
operating, otherwise the responses conflict. This must be enforced by software.
18.2.31
DPLBASE—DMA Position Lower Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 70h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer Base
31:7
Address. This register field must not be written when any DMA engine is running or the DMA
transfer may be corrupted. This same address is used by the Flush Control and must be
programmed with a valid value before the Flush Control bit (HDBAR+08h:bit 1) is set.
6:1
DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128-byte buffer
alignment for cache line write optimizations.
DMA Position Buffer Enable — R/W.
0 ^{When this bit is set to 1, the controller will write the DMA positions of each of the DMA engines to the}
buffer in the main memory periodically (typically once per frame). Software can use this value to
know what data in memory is valid data.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet