82801FB Datasheet, PDF (411/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.3.9
PM2_CNT—Power Management 2 Control (Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI
Bit
Description
7:1 ^Reserved
Arbiter Disable (ARB_DIS) — R/W. This bit is essentially just a scratchpad bit for legacy software
compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state. When a transition
to a C3 or C4 state occurs, ICH6 will automatically prevent any internal or external non-Isoch bus
0 ^{masters from initiating any cycles up to the (G)MCH. This blocking starts immediately upon the ICH6}
sending the Go-C3 message to the (G)MCH. The blocking stops when the Ack-C2 message is
received. Note that this is not really blocking, in that messages (such as from PCI Express*) are just
queued and held pending.
10.8.3.10 GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 28h
(ACPI GPE0_BLK)
00000000h
No
Resume
Attribute:
Size:
Usage:
R/W, R/WC
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless indicated
otherwise below, if the corresponding _EN bit is set, then when the _STS bit get set, the ICH6 will
generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event
occurs), the ICH6 will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit
(PMBASE + 04h, bit 0) is not set. Bits 31:16 are reset by a CF9h write; bits 15:0 are not. All are
reset by RSMRST#.
Bit
31:16
15
14
Description
GPIn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the
corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is
set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPI_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPI[15] ... and bit 16 corresponds to GPI:[0].
Reserved
USB4_STS — R/W.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset.
This bit is set when USB UHCI controller #4 needs to cause a wake. Additionally if the
USB4_EN bit is set, the setting of the USB4_STS bit will generate a wake event.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
411