82801FB Datasheet, PDF (570/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.1
HST_STS—Host Status Register (SMBus—D31:F3)
Register Offset: SMBASE + 00h
Default Value: 00h
Attribute:
Size:
R/WC, R/WC (special), RO
8-bits
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position. Writing a 0 to any bit position has no effect.
Bit
Description
Byte Done Status (DS) — R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed transmission
of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this
bit will be set, even on the last byte of the transfer. This bit is not set when transmission is due
to the LAN interface heartbeat.
7 ^{This bit has no meaning for block transfers when the 32-byte buffer is enabled.}
NOTE: When the last byte of a block message is received, the host controller will set this bit.
However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt
handler clears the DS bit, the message is considered complete, and the host controller will
then set the INTR bit (and generate another interrupt). Thus, for a block message of n
bytes, the ICH6 will generate n+1 interrupts. The interrupt handler needs to be implemented
to handle these cases.
INUSE_STS — R/WC (special). This bit is used as semaphore among various independent software
threads that may need to use the ICH6’s SMBus logic, and has no other effect on hardware.
6 ^{0 = After a full PCI reset, a read to this bit returns a 0.}
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
SMBALERT_STS — R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to
5
it.
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by
software writing a 1 to the bit position or by RSMRST# going low.
If the signal is programmed as a GPI, then this bit will never be set.
FAILED — R/WC.
4 ^{0 = Software clears this bit by writing a 1 to it.}
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
the KILL bit being set to terminate the host transaction.
BUS_ERR — R/WC.
3 _{0 = Software clears this bit by writing a 1 to it.}
1 = The source of the interrupt of SMI# was a transaction collision.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet