82801FB Datasheet, PDF (118/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)
The ICH6 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-6 shows the valid bit encodings.
Table 5-6. Cycle Type Bit Definitions
Bits[3:2]
Bit1
Definition
00
0
I/O Read
00
1
I/O Write
01
0
Memory Read
01
1
Memory Write
10
0
DMA Read
10
1
DMA Write
11
x
Reserved. If a peripheral performing a bus master cycle generates this value, the
Intel^® ICH6 aborts the cycle.
5.5.1.4 SIZE
Bits[3:2] are reserved. The ICH6 always drives them to 00. Peripherals running bus master cycles
are also supposed to drive 00 for bits 3:2; however, the ICH6 ignores those bits. Bits[1:0] are
encoded as listed in Table 5-7.
Table 5-7. Transfer Size Bit Definition
Bits[1:0]
00
01
10
11
Size
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel^® ICH6 never drives this combination. If a peripheral running a bus
master cycle drives this combination, the ICH6 may abort the transfer.
32-bit transfer (4 bytes)
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet