82801FB Datasheet, PDF (301/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.2.8
EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0)
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Early Receive Interrupt register allows the internal LAN controller to generate an early
interrupt depending on the length of the frame. The LAN controller will generate an interrupt at the
end of the frame regardless of whether or not Early Receive Interrupts are enabled.
Note:
It is recommended that software not use this register unless receive interrupt latency is a critical
performance issue in that particular software environment. Using this feature may reduce receive
interrupt latency, but will also result in the generation of more interrupts, which can degrade
system efficiency and performance in some environments.
Bit
Description
Early Receive Count — R/W. When some non-zero value x is programmed into this register, the
LAN controller will set the ER bit in the SCB Status Word Register and assert INTA# when the byte
7:0 count indicates that there are x QWords remaining to be received in the current frame (based on the
Type/Length field of the received frame). No Early Receive interrupt will be generated if a value of
00h (the default value) is programmed into this register.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
301