82801FB Datasheet, PDF (614/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Modem Controller Registers (D30:F3)
17.1.16
INT_PIN—Interrupt Pin Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
3Dh
See description
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
This register indicates which PCI interrupt pin is used for the AC ’97 modem interrupt. The AC ’97
interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
Bit
Description
7:3 Reserved
2:0 Interrupt Pin (INT_PN) — RO. This reflects the value of D30IP.AMIP in chipset configuration space.
17.1.17
PID—PCI Power Management Capability Identification
Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
50h
0001h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
15:8 Next Capability (NEXT) — RO. This field indicates that this is the last item in the list.
7:0
Capability ID (CAP) — RO. This field indicates that this pointer is a message signaled interrupt
capability.
17.1.18
PC—Power Management Capabilities Register
(Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
52h
C9C2h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
15:11
10:9
8:6
5
4
3
2:0
PME Support — RO. This field indicates PME# can be generated from all D states.
Reserved.
Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current required when in
the D3_COLD state.
Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific initialization is
required.
Reserved — RO.
PME Clock (PMEC) — RO. This bit indicates that PCI clock is not required to generate PME#.
Version (VS) — RO. This field indicates support for Revision 1.1 of the PCI Power Management
Specification.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet