82801FB Datasheet, PDF (482/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h–E7h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of
the second DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its
31:0
contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST
FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”,
this register’s contents will be transmitted as the BIST FIS 2nd DW regardless of whether or not the
“T” bit is indicated in the BFCS register (D31:F2:E0h).
12.1.45 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h–EBh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form the contents of
the third DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its contents
31:0
will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are
only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”, this
register’s contents will be transmitted as the BIST FIS 3rd DW regardless of whether or not the “T” bit
is indicated in the BFCS register (D31:F2:E0h).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet