82801FB Datasheet, PDF (581/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Audio Controller Registers (D30:F2)
16 AC ’97 Audio Controller Registers
(D30:F2)
16.1 AC ’97 Audio PCI Configuration Space
(Audio—D30:F2)
Note: Registers that are not shown should be treated as Reserved.
Table 16-1. AC ‘97 Audio PCI Register Address Map (Audio—D30:F2)
Offset
00–01h
02–03h
04–05h
06–07h
Mnemonic
Register Name
VID
Vendor Identification
DID
PCICMD
PCISTS
Device Identification
PCI Command
PCI Status
08h
RID
Revision Identification
09h
0Ah
0Bh
0Eh
10–13h
14–17h
18–1Bh
1C–1Fh
2C–2Dh
2E–2Fh
34h
3Ch
PI
SCC
BCC
HEADTYP
NAMBBAR
NAMMBAR
MMBAR
MBBAR
SVID
SID
CAP_PTR
INT_LN
Programming Interface
Sub Class Code
Base Class Code
Header Type
Native Audio Mixer Base Address
Native Audio Bus Mastering Base Address
Mixer Base Address (Mem)
Bus Master Base Address (Mem)
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
Interrupt Line
3Dh
INT_PN Interrupt Pin
40h
41h
50–51h
52–53h
54–55h
PCID
CFG
PID
PC
PCS
Programmable Codec ID
Configuration
PCI Power Management Capability ID
PC -Power Management Capabilities
Power Management Control and Status
Default
8086h
266Eh
0000h
0280h
See register
description
00
01h
04h
00h
00000001h
00000001h
00000000h
00000000h
0000h
0000h
50h
00h
See register
description
09h
00h
0001h
C9C2h
0000h
Access
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WO
R/WO
RO
R/W
RO
R/W
R/W
RO
RO
R/W, R/WC
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0
transition. All resume well registers will not be reset by the D3_HOT to D0 transition.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
581