82801FB Datasheet, PDF (19/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
11.1.11 PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1).......................................................................................442
11.1.12 PCNL_BAR—Primary Control Block Base Address
Register (IDE—D31:F1).......................................................................................443
11.1.13 SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) .........................................................................................443
11.1.14 SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) .........................................................................................443
11.1.15 BM_BASE — Bus Master Base Address Register
(IDE—D31:F1) .....................................................................................................444
11.1.16 IDE_SVID — Subsystem Vendor Identification
(IDE—D31:F1) .....................................................................................................444
11.1.17 IDE_SID — Subsystem Identification Register
(IDE—D31:F1) .....................................................................................................444
11.1.18 INTR_LN—Interrupt Line Register (IDE—D31:F1) ..............................................445
11.1.19 INTR_PN—Interrupt Pin Register (IDE—D31:F1) ...............................................445
11.1.20 IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1) ................................445
11.1.21 IDE_TIMS — IDE Secondary Timing Register
(IDE—D31:F1) .....................................................................................................447
11.1.22 SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1) .....................................................................................................447
11.1.23 SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1) .....................................................................................................448
11.1.24 SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1) .....................................................................................................449
11.1.25 IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1) .....................................................................................................450
11.1.26 ATC—APM Trapping Control Register (IDE—D31:F1) .......................................451
11.1.27 ATS—APM Trapping Status Register (IDE—D31:F1) .........................................451
11.2 Bus Master IDE I/O Registers (IDE—D31:F1) ..................................................................451
11.2.1 BMICP—Bus Master IDE Command Register
(IDE—D31:F1) .....................................................................................................452
11.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1)...................................453
11.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register
(IDE—D31:F1) .....................................................................................................453
12 SATA Controller Registers (D31:F2)............................................................................455
12.1 PCI Configuration Registers (SATA–D31:F2)...................................................................455
12.1.1 VID—Vendor Identification Register (SATA—D31:F2) ........................................456
12.1.2 DID—Device Identification Register (SATA—D31:F2) ........................................457
12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)...........................................457
12.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ................................................458
12.1.5 RID—Revision Identification Register (SATA—D31:F2)......................................458
12.1.6 PI—Programming Interface Register (SATA–D31:F2) ........................................459
12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ...............459
12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ...............459
12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ...............460
12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)...............................................460
12.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2) ............................................................................460
12.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F2) ...................................................................................................461
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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