82801FB Datasheet, PDF (10/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
5.22.2.1 Register Access ................................................................................... 230
5.22.3 AC-Link Low Power Mode ................................................................................... 231
5.22.3.1 External Wake Event ........................................................................... 232
5.22.4 AC ’97 Cold Reset ............................................................................................... 233
5.22.5 AC ’97 Warm Reset ............................................................................................. 233
5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec............................... 233
5.23 Intel® High Definition Audio (D27:F0) .............................................................................. 234
5.23.1 Link Protocol Overview ........................................................................................ 234
5.23.1.1 Frame Composition.............................................................................. 234
5.23.2 Link Reset............................................................................................................ 235
5.23.3 Link Power Management ..................................................................................... 235
6 Register and Memory Mapping...................................................................................... 237
6.1 PCI Devices and Functions .............................................................................................. 238
6.2 PCI Configuration Map ..................................................................................................... 239
6.3 I/O Map ............................................................................................................................. 239
6.3.1 Fixed I/O Address Ranges................................................................................... 239
6.3.2 Variable I/O Decode Ranges ............................................................................... 242
6.4 Memory Map..................................................................................................................... 243
6.4.1 Boot-Block Update Scheme................................................................................. 244
7 Chipset Configuration Registers .................................................................................. 247
7.1 Chipset Configuration Registers (Memory Space) ........................................................... 247
7.1.1 VCH—Virtual Channel Capability Header Register ............................................. 249
7.1.2 VCAP1—Virtual Channel Capability #1 Register................................................. 249
7.1.3 VCAP2—Virtual Channel Capability #2 Register................................................. 250
7.1.4 PVC—Port Virtual Channel Control Register....................................................... 250
7.1.5 PVS—Port Virtual Channel Status Register ........................................................ 250
7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register .................................. 251
7.1.7 V0CTL—Virtual Channel 0 Resource Control Register ....................................... 251
7.1.8 V0STS—Virtual Channel 0 Resource Status Register ........................................ 252
7.1.9 RCTCL—Root Complex Topology Capabilities List Register .............................. 252
7.1.10 ESD—Element Self Description Register ............................................................ 252
7.1.11 ULD—Upstream Link Descriptor Register ........................................................... 253
7.1.12 ULBA—Upstream Link Base Address Register................................................... 253
7.1.13 RP1D—Root Port 1 Descriptor Register.............................................................. 253
7.1.14 RP1BA—Root Port 1 Base Address Register ..................................................... 254
7.1.15 RP2D—Root Port 2 Descriptor Register.............................................................. 254
7.1.16 RP2BA—Root Port 2 Base Address Register ..................................................... 254
7.1.17 RP3D—Root Port 3 Descriptor Register.............................................................. 255
7.1.18 RP3BA—Root Port 3 Base Address Register ..................................................... 255
7.1.19 RP4D—Root Port 4 Descriptor Register.............................................................. 255
7.1.20 RP4BA—Root Port 4 Base Address Register ..................................................... 256
7.1.21 HDD—Intel^® High Definition Audio Descriptor Register ...................................... 256
7.1.22 HDBA—Intel^® High Definition Audio Base Address Register .............................. 256
7.1.23 ILCL—Internal Link Capabilities List Register ..................................................... 257
7.1.24 LCAP—Link Capabilities Register ....................................................................... 257
7.1.25 LCTL—Link Control Register............................................................................... 257
7.1.26 LSTS—Link Status Register ................................................................................ 258
7.1.27 CSIR5—Chipset Initialization Register 5 ............................................................. 258
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet