82801FB Datasheet, PDF (219/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.21.3
5.21.3.1
5.21.3.2
Bus Timing
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH6 as an SMBus
master would like. They have the capability of stretching the low time of the clock. When the ICH6
attempts to release the clock (allowing the clock to go high), the clock will remain low for an
extended period of time.
The ICH6 monitors the SMBus clock line after it releases the bus to determine whether to enable
the counter for the high time of the clock. While the bus is still low, the high time counter must not
be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not
ready to send or receive data.
Bus Time Out (Intel^® ICH6 as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge,
or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH6
will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC
clocks). The time-out counter inside the ICH6 will start after the last bit of data is transferred by the
ICH6 and it is waiting for a response.
The 25 ms timeout counter will not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the
system has not locked up)
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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