82801FB Datasheet, PDF (275/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
Bit
Description
No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on ICH6) is
sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low
but may not override the strap when it indicates “No Reboot”.
5
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot
on the second timeout.
Alternate Access Mode Enable (AME) — R/W.
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can be read.
4
Before entering a low power state, several registers from powered down parts may need to
be saved. In the majority of cases, this is not an issue, as registers have read and write
paths. However, several of the ISA compatible registers are either read only or write only. To
get data out of write-only registers, and to restore data into read-only registers, the ICH
implements an alternate access mode. For a list of these registers see Section 5.14.10.
Boot BIOS Destination (BBD) — R/W. The default value of this bit is determined by a strap
allowing systems with corrupted or unprogrammed flash to boot from a PCI device. The value of
the strap can be overwritten by software.
When this bit is 0, the PCI-to-PCI bridge memory space enable bit does not need to be set (nor
any other bits) in order for these cycles to go to PCI. Note that BIOS enable ranges and the other
BIOS protection and update bits associated with the FWH interface have no effect when this bit is
3
0.
0 = The top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is accepted by the
primary side of the PCI P2P bridge and forwarded to the PCI bus.
1 = The top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is not decoded to PCI
and the LPC bridge claims these cycles based on the FWH Decode Enable bits.
NOTE: This functionality intended for debug/testing only.
Reserved Page Route (RPR) — R/W. Determines where to send the reserved page registers.
These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O
addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh.
0 = Writes will be forwarded to LPC, shadowed within the ICH, and reads will be returned from
the internal shadow
1 = Writes will be forwarded to PCI, shadowed within the ICH, and reads will be returned from
2
the internal shadow.
Note, if some writes are done to LPC/PCI to these I/O ranges, and then this bit is flipped, such
that writes will now go to the other interface, the reads will not return what was last written.
Shadowing is performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always
decoded to LPC.
1
Reserved
Top Swap Lock-Down (TSLD) — R/WLO.
0
0 = Disabled.
1 = Prevents BUC.TS (offset 3414, bit 0) from being changed. This bit can only be written from 0
to 1 once.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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