82801FB Datasheet, PDF (458/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)
Address Offset: 06–07h
Default Value: 02B0h
Attribute: R/WC, RO
Size:
16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 _{0 = No parity error detected by SATA controller.}
1 = SATA controller detects a parity error on its interface.
14 Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
13 _{0 = Master abort Not generated.}
1 = SATA controller, as a master, generated a master abort.
12 Reserved as 0 — RO.
11 Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED) — RO. For ICH6, this bit can only be set on read completions
8
received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted,
and the parity error response bit (bit 6 of the command register) is set.
7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
6 User Definable Features (UDF) — RO. Reserved as 0.
5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The
4 minimum requirement for the capabilities list must be PCI power management for the SATA
controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.
3
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register
[offset 04h]).
1 = Interrupt is to be asserted
2:0 Reserved
12.1.5
RID—Revision Identification Register (SATA—D31:F2)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 6 (ICH6) Family Specification Update for
the value of the Revision ID Register
458
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet