82801FB Datasheet, PDF (365/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.2.5
10.2.6
DMASTA—DMA Status Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 08h;
Ch. #4–7 = D0h
Undefined
No
Attribute:
Size:
Power Well:
RO
8-bit
Core
Bit
Description
Channel Request Status — RO. When a valid DMA request is pending for a channel, the
corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the
corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note
that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the
request status for channels 0 through 3.
7:4
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
Channel Terminal Count Status — RO. When a channel reaches terminal count (TC), its status bit
is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for
cascade, so the TC bit response for channel 4 is irrelevant:
3:0 ^{0 = Channel 0}
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Ah;
Ch. #4–7 = D4h
0000 01xx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:3 Reserved. Must be 0.
Channel Mask Select — WO.
2 ^{0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore,}
only one channel can be masked / unmasked at a time.
1 = Disable DREQ for the selected channel.
DMA Channel Select — WO. These bits select the DMA Channel Mode Register to program.
00 = Channel 0 (4)
1:0 01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
365